发明名称 Maskless hybrid laser scribing and plasma etching wafer dicing process
摘要 Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.
申请公布号 US9209084(B2) 申请公布日期 2015.12.08
申请号 US201414454656 申请日期 2014.08.07
申请人 Applied Materials, Inc. 发明人 Lei Wei-Sheng;Eaton Brad;Papanu James S.;Kumar Ajay
分类号 H01L21/00;H01L21/78;H01L21/3065;H01L21/82;B23K26/00;B23K26/06 主分类号 H01L21/00
代理机构 Blakely Sokoloff Taylor Zafman LLP 代理人 Blakely Sokoloff Taylor Zafman LLP
主权项 1. A method of dicing a silicon wafer comprising a front surface having a plurality of DRAM circuits thereon and having a polyimide layer disposed between and covering metal pillar/solder bump pairs of the DRAM circuits, the method comprising: laser scribing, without the use of a mask layer, the polyimide layer to provide scribe lines exposing the silicon wafer, the laser scribing performed through a layer of low K material and a layer of copper both disposed between the polyimide layer and the silicon substrate, the laser scribing comprising a femto-second-based laser scribing process; plasma etching the silicon wafer through the scribe lines to singulate the DRAM circuits, wherein the polyimide layer protects the DRAM circuits during at least a portion of the plasma etching; and plasma ashing the polyimide layer to thin the polyimide layer, partially exposing the metal pillar/solder bump pairs of the DRAM circuits.
地址 Santa Clara CA US