Methods for fabricating integrated circuits using self-aligned quadruple patterning

摘要

Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

主权项

1. A method for fabricating an integrated circuit, the method comprising:
providing a patternable structure having a first region and second region and including an upper mandrel layer overlying a lower mandrel layer; etching upper mandrels from the upper mandrel layer in the first region and in the second region of the patternable structure; forming first upper spacer structures having a first width adjacent the upper mandrels in the first region; forming second upper spacer structures having a second width not equal to the first width adjacent the upper mandrels in the second region; etching the lower mandrel layer using the first upper spacer structures and the second upper spacer structures as a first etch mask to form lower mandrels; forming lower spacers adjacent the lower mandrels; and etching a material using the lower spacers as a second etch mask to form variably spaced features.