SHIFT REGISTER AND METHOD OF DRIVING THE SAME, AND GROUP OF SHIFT REGISTERS AND METHOD OF DRIVING THE SAME

摘要

A shift register circuit is disclosed. In some embodiments, the shift register circuit includes six transistors and no capacitors. A group of such shift register circuits is also disclosed. In some embodiments, the shift registers of the group are connected so as to be configured to provide driving signals for a display. A method of using the shift registers is also disclosed.

主权项

1. A shift register, comprising:
a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a sixth transistor, wherein:
a gate of the first transistor is connected to a first clock signal terminal, a source of the first transistor is connected to a first input signal terminal, and a drain of the first transistor is connected to a source of the second transistor and a gate of the sixth transistor,a gate of the second transistor is connected to a first level signal terminal, the source of the second transistor is connected to the drain of the first transistor and the gate of the sixth transistor, and a drain of the second transistor is connected to a gate of the third transistor,the gate of the third transistor is connected to the drain of the second transistor, a source of the third transistor is connected to a second clock signal terminal, and a drain of the third transistor is connected to an output terminal and a drain of the fifth transistor,a gate of the fourth transistor is connected to a source of the fourth transistor, the gate and the source of the fourth transistor are connected to a second input signal terminal, and a drain of the fourth transistor is connected to a gate of the fifth transistor and a drain of the sixth transistor,the gate of the fifth transistor is connected to the drain of the fourth transistor and the drain of the sixth transistor, a source of the fifth transistor is connected to a second level signal terminal and a source of the sixth transistor, and the drain of the fifth transistor is connected to the output terminal and the drain of the third transistor, andthe gate of the sixth transistor is connected to the drain of the first transistor and the source of the second transistor, the source of the sixth transistor is connected to the second level signal terminal and the source of the fifth transistor, and the drain of the sixth transistor is connected to the drain of the fourth transistor and the gate of the fifth transistor.