LOW PARASITIC CAPACITANCE SEMICONDUCTOR DEVICE PACKAGE

摘要

A semiconductor device package includes a substrate, a transistor, and a lead frame disposed on a side of the substrate opposite to the transistor. The transistor is disposed on the substrate, and includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, a first drain pad, a source plug, and a drain plug. The source and the drain electrodes are disposed on the active layer. An orthogonal projection of the source electrode on the active layer forms a source region. The first insulating layer covers at least a portion of the source electrode and at least a portion of the drain electrode. The first source pad and the first drain pad are disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region overlaps the drain region.

主权项

1. A semiconductor device package, comprising:
a substrate; a transistor disposed on the substrate, comprising:
an active layer;at least one source electrode disposed on the active layer, and an orthogonal projection of the source electrode on the active layer forming a source region;at least one drain electrode disposed on the active layer, the drain electrode separated from the source electrode, and an orthogonal projection of the drain electrode on the active layer forming a drain region;at least one gate electrode disposed on the active layer and between the source electrode and the drain electrode;a first insulating layer covering at least a portion of the source electrode and at least a portion of the drain electrode, the first insulating layer having at least one source via hole and at least one drain via hole therein;a first source pad disposed on the first insulating layer, and an orthogonal projection of the first source pad on the active layer forming a source pad region, the source pad region overlapping at least a portion of the drain region, and an area of overlapping region between the source pad region and the drain region being smaller than or equal to 40% of an area of the drain region;a first drain pad disposed on the first insulating layer;at least one source plug filled in the source via hole and electrically connected to the first source pad and the source electrode; andat least one drain plug filled in the drain via hole and electrically connected to the first drain pad and the drain electrode; and a lead frame disposed on a side of the substrate opposite to the transistor and electrically connected to the gate electrode.