The present invention relates to a gate driving circuit. A timing signal input terminal of a first stage is connected to a timing signal output terminal of a third stage. A carry terminal of a second stage is connected to an input terminal of the third stage. The second stage includes: an input unit which receives a carry signal from the first stage, a bootstrapping unit which applies a clock signal of a first voltage level to a first node according to the level of the carry signal, a first pull-down unit which is connected to the first node and a first ground terminal, and a second pull-down unit which is connected to the first node. The gate driving circuit according to the embodiment of the present invention improves the efficiency of an output signal by reducing a ripple phenomenon in the output signal.
申请公布号
KR20150131455(A)
申请公布日期
2015.11.25
申请号
KR20140057900
申请日期
2014.05.14
申请人
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE;KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.
发明人
PI, JAE EUN;PARK, KEE CHAN;LEE, JAE WON;KWON, OH SANG;PARK, SANG HEE;RYU, MIN KI;KIM, JONG WOO;YU, BYOUNG GON;HWANG, CHI SUN