Apparatus and method of controlling clock signals

摘要

An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

主权项

1. A controlling apparatus for a master device and a slave device comprising:
a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; a ground port; and a high-level bias port, coupled to a voltage source via a pull-up impedance; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval, and the control module connects the first connection port to the ground port or the high-level bias port to maintain the second logic level.