SEMICONDUCTOR MEMORY DEVICE PERFORMING SELF-REPAIR OPERATION

摘要

A semiconductor memory device includes a memory cell array including a main cell array and a repair cell array, a command controller that controls an input/output operation of the memory cell array, an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written, an ECC that performs a parity operation for data input/output to the memory cell array, an address table that associates an address, at which a fail has occurred when the fail has occurred in the ECC, with a number of times of occurrence of the fail, and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored.

主权项

1. A semiconductor memory device comprising:
a memory cell array including a main cell array and a repair cell array; a command controller that controls an input/output operation of the memory cell array according to a read or write request; an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written; an ECC that performs a parity operation for data input/output to the memory cell array; an address table that associates an address, at which a fail has occurred when the fail has occurred in the ECC, with a number of times of occurrence of the fail, and stores the associated address and the number of times of the occurrence of the fail; and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored.