发明名称 半導体試料中の金属汚染評価方法および半導体基板の製造方法
摘要 An aspect of the present invention relates to a method of evaluating metal contamination in a semiconductor sample by DLTS method, which includes obtaining a first DLTS spectrum by measuring a DLTS signal while varying a temperature, the DLTS signal being generated by alternatively and cyclically applying to a semiconductor junction on a semiconductor sample a reverse voltage VR to form a depletion layer and a weak voltage V1 to trap carriers in the depletion layer; obtaining a second DLTS spectrum by measuring a DLTS signal while varying a temperature, the DLTS signal is being generated by cyclically applying the VR to the semiconductor junction; obtaining a differential spectrum of the first DLTS spectrum with a correction-use spectrum in the form of the second DLTS spectrum or a spectrum that is obtained by approximating the second DLTS spectrum as a straight line or as a curve.
申请公布号 JP5817236(B2) 申请公布日期 2015.11.18
申请号 JP20110135382 申请日期 2011.06.17
申请人 株式会社SUMCO 发明人 松本 圭;大野 隆司
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
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