HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE

摘要

An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

主权项

1. An integrated circuit having a p-channel high-voltage metal oxide semiconductor (MOS) transistor and an n-channel high-voltage MOS transistor, comprising:
a substrate comprising a p-type semiconductor; an n-type n-channel metal oxide semiconductor (NMOS) drain extension and an n-type NMOS source extension of said n-channel high-voltage MOS transistor; an n-type p-channel metal oxide semiconductor (PMOS) threshold adjustment region of said p-channel high-voltage MOS transistor, said PMOS threshold adjustment region being electrically coupled to an n-type buried layer; a high-voltage gate dielectric layer at a top surface of said substrate in said p-channel high-voltage MOS transistor and in said n-channel high-voltage MOS transistor; a p-type NMOS threshold adjustment region of said n-channel high-voltage MOS transistor; a PMOS drain extension and a PMOS source extension of said p-channel high-voltage MOS transistor; and a high-voltage PMOS gate of said p-channel high-voltage MOS transistor and a high-voltage NMOS gate of said n-channel high-voltage MOS transistor; such that: said high-voltage PMOS gate has a drain-centered closed loop configuration; said high-voltage PMOS gate does not overlap said field oxide; said high-voltage NMOS gate has a drain-centered closed loop configuration; said high-voltage NMOS gate does not overlap said field oxide; said PMOS drain extension is free of said field oxide; said PMOS source extension between a PMOS source contact region and said PMOS threshold adjustment region is free of said field oxide; said NMOS drain extension is free of said field oxide; and said NMOS source extension between a NMOS source contact region and said NMOS threshold adjustment region is free of said field oxide.