发明名称 METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES
摘要 Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.
申请公布号 US2015325467(A1) 申请公布日期 2015.11.12
申请号 US201414272787 申请日期 2014.05.08
申请人 GLOBALFOUNDRIES, Inc. 发明人 Zhang Xunyuan;Bolom Tibor;Ahn Kun Ho;Hintze Bernd;Koschinsky Frank
分类号 H01L21/768;H01L21/285 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method for fabricating an integrated circuit, the method comprising: forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process, wherein the barrier layer has a lower portion and a densified upper portion that has a greater density than the lower portion; depositing a liner-forming material overlying the barrier layer to form a liner; and depositing a conductive metal overlying the liner.
地址 Grand Cayman KY