Method and arrangement for suppressing interferences in the useful frequency band of an analog output signal

摘要

A first parallelized digital data signal (DS21) with single data signals (D100-D115) transmitted parallel to each other is converted into a second parallelized digital data signal (DS22) with single data signals (D200-D214) in a first number of parallel lines (FNOPL), chosen as unequal to the FNOPL. First and second parallelized data signals have an equal clock frequency (fDATA2). Independent claims are also included for the following: (A) A device for adapting data rates; (B) and for a system for curbing unwanted signals in a wanted signal frequency range for an analog output signal with a device for adapting data rates.