发明名称 |
Circuits for and methods of implementing a charge/discharge switch in an integrated circuit |
摘要 |
A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described. |
申请公布号 |
US9184623(B1) |
申请公布日期 |
2015.11.10 |
申请号 |
US201514694862 |
申请日期 |
2015.04.23 |
申请人 |
XILINX, INC. |
发明人 |
Cical Ionut C.;Jennings John K. |
分类号 |
H03L7/06;H02J7/34;H02J7/00;H03K17/56 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
King John J. |
主权项 |
1. A circuit for implementing a charge/discharge switch in an integrated circuit, the circuit comprising:
a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. |
地址 |
San Jose CA US |