发明名称 Dynamic on/off just-in-time compilation in a dynamic translator using instruction code translation
摘要 Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.
申请公布号 US9183018(B2) 申请公布日期 2015.11.10
申请号 US201314143297 申请日期 2013.12.30
申请人 发明人 Jennings Andrew T;Caldarale Charles R;Heimann Gregory;Marks Maurice;Harris Kevin
分类号 G06F9/44;G06F9/455 主分类号 G06F9/44
代理机构 代理人 Gregson Richard J.
主权项 1. A method for dynamically turning on or off just-in-time compilation in a dynamic translator using instruction code translation, comprising: fetching a non-native instruction from a plurality of non-native instructions; interpreting the non-native instruction to generate an instruction code; determining if the instruction code satisfies a criteria which prohibits compilation of the instruction code; and when the criteria is determined to be satisfied: prohibiting compilation of the instruction code; andimplementing a virtual machine instruction corresponding to the non-native instruction based, at least in part, on the instruction code if the criteria is determined to be satisfied; wherein the criteria comprises a range of addresses in at least one of a shadow memory associated with the plurality of non-native instructions and a non-native memory, and the step of determining if the criteria is satisfied comprises at least one of determining if the instruction code is located within the range of addresses in the shadow memory and determining if the non-native instruction is located within the non-native memory.
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