| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock circuit that reduces power consumption further when one of clock domains having clock tree circuits with different numbers of stages, respectively, is powered down.SOLUTION: If a second clock tree circuit 21 of a second clock domain 2 has a larger number of stages than a first clock tree circuit 11 of a first clock domain 1, a selection circuit 13 selects a clock signal output from a delay circuit 23 to be input into the first clock tree circuit 11 when the second clock domain 2 is powered up, and selects an original clock signal to be input into the first clock tree circuit 11 when the second clock domain 2 is powered down.</p> |
