ARRAY SUBSTRATE AND DISPLAY DEVICE

摘要

An array substrate and a display device are provided. The array substrate comprises a display region and a peripheral circuit region (B), wherein a first gate line (20), a first data line (10) and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region (B) is provided with at least one test unit (100) including: a second gate line (101); a second data line (102); a second testing pixel electrode (103); and a second testing thin film transistor (104). The second testing thin film transistor (104) comprises a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.

主权项

1. An array substrate, comprising a display region and a peripheral circuit region located outside the display region, wherein a plurality of first gate lines, a plurality of first data lines and a plurality of pixel regions surrounded by the first gate lines and the first data lines are arranged in the display region; each pixel region includes a first pixel electrode and a first thin film transistor, and the first thin film transistor includes a first gate electrode connected to the first gate line, a first source electrode connected to the first data line and a first drain electrode connected to the pixel electrode; wherein the array substrate further comprises at least one test unit arranged in the peripheral circuit region, the test unit comprises:
a second gate line and a second data line intersecting with each other, wherein when the array substrate is in a working state, a signal inputted to the second gate line is identical with a signal inputted to a corresponding first gate line, and a signal inputted to the second data line is identical with a signal inputted to a corresponding first data line; a second testing pixel electrode arranged close to an intersection of the second gate line and the second data line; a second testing thin film transistor arranged at the intersection of the second gate line and the second data line, wherein the second testing thin film transistor includes a second gate electrode connected to the second gate line, a second source electrode connected to the second data line and a second drain electrode connected to the second testing pixel electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.