发明名称 |
Integrated circuits having cascode transistor |
摘要 |
An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor. |
申请公布号 |
US9170596(B2) |
申请公布日期 |
2015.10.27 |
申请号 |
US201414301409 |
申请日期 |
2014.06.11 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Lin Yvonne |
分类号 |
G05F1/10;H03K3/01;G05F3/24;H01L25/03 |
主分类号 |
G05F1/10 |
代理机构 |
Hauptman Ham, LLP |
代理人 |
Hauptman Ham, LLP |
主权项 |
1. An integrated circuit comprising:
a first circuit, the first circuit comprising:
a first transistor having a first dopant type;a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor, and a gate of the first transistor is connected to a gate of the first cascode transistor;a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor, and a gate of the second transistor is configured to receive a first input signal;a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor; anda third transistor having the second dopant type, wherein a source of the third transistor is connected to a source of the second transistor, and a gate of the third transistor is configured to receive a second input signal different from the first input signal; and a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor. |
地址 |
TW |