VERTICAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE

摘要

Aspects of the invention are directed to a vertical semiconductor device including an element active portion and a voltage withstanding structure portion has a first main electrode and a gate pad electrode on a first main surface of the element active portion, includes first parallel pn layers in a drift layer below the first main electrode, and includes second parallel pn layers below the gate pad electrode. The vertical semiconductor device includes a first conductivity type isolation region between the second parallel pn layers below the gate pad electrode and a p-type well region disposed in a surface layer of the drift layer, and by the repetition pitch of the second parallel pn layers being shorter than the repetition pitch of the first parallel pn layers, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand.

主权项

1. A vertical semiconductor device comprising an element active portion and a voltage withstanding structure portion, the element active portion including:
a first conductivity type first semiconductor layer; a drift layer disposed on a first main surface of the first semiconductor layer; a first conductivity type second semiconductor layer disposed in a surface layer of the drift layer; a second conductivity type well region disposed in a surface layer of the second semiconductor layer; a first conductivity type source region disposed in a surface layer of the well region; a second conductivity type contact region disposed in a surface layer of the well region; a gate electrode disposed across a gate insulating film above the well region sandwiched between the source region of the well region and the second semiconductor layer; an interlayer dielectric disposed on the upper surface of the gate electrode; a first main electrode electrically connected to the source region and contact region on the upper surface of the interlayer dielectric; and a gate pad electrode, to which the gate electrode is electrically connected, disposed separated from the first main electrode on the upper surface of the interlayer dielectric, wherein the drift layer below the first main electrode includes first parallel pn layers wherein a first first conductivity type semiconductor region and first second conductivity type semiconductor region are repeatedly alternately disposed in a direction parallel to the first main surface and the first second conductivity type semiconductor region is in contact with the well region, the drift layer below the gate pad electrode includes second parallel pn layers wherein a second first conductivity type semiconductor region and second second conductivity type semiconductor region are repeatedly alternately disposed in a direction parallel to the first main surface and the second second conductivity type semiconductor region is disposed so as to oppose the well region, and a first conductivity type isolation region is included between the second parallel pn layers and the well region.