| 主权项 |
1. A clock signal controller, comprising:
a first transistor, one of a source and a drain of the first transistor being connected to a working level, the other of the source and the drain of the first transistor being connected to a first connecting point, and a gate of the first transistor being connected to a first clock signal input end; a second transistor, one of a source and a drain of the second transistor being connected to a first connecting point, the other of the source and the drain of the second transistor being connected to a reference level, and a gate of the second transistor being connected to the first clock signal input end; a third transistor, one of a source and a drain of the third transistor being connected to the working level, the other of the source and the drain of the third transistor being connected to a second connecting point, and a gate of the third transistor being connected to a second clock signal input end; and a fourth transistor, one of a source and a drain of the fourth transistor being connected to the working level, the other of the source and the drain of the fourth transistor being connected to the second connecting point, and a gate of the fourth transistor being connected to the second clock signal input end; wherein the first connecting point and the second connecting point are connected to a first clock signal output end; wherein the first transistor and the second transistor are complementary type transistors, and wherein the third transistor and the fourth transistor are complementary type transistors. |
