| 主权项 |
1. A relaxation oscillator, comprising:
a S-R flip flop, comprising a S input terminal, a R input terminal, a Q terminal and a Q′ terminal; a first delay circuit, comprising:
a first charging circuit, comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first charging circuit is coupled to a power voltage, the control terminal of the first charging circuit is coupled to the Q terminal, wherein the first terminal of the first charging circuit is electrically conducted with the second terminal of the first charging circuit when the Q terminal outputs a first logic voltage;a first capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the second terminal of the first charging circuit, and the second terminal of the first capacitor is coupled to a common voltage;a first discharging device, comprising a first terminal and a second terminal, wherein the first terminal of the first discharging device is coupled to the second terminal of the first charging circuit, and the second terminal of the first discharging device is coupled to the common voltage; anda first comparing/detecting circuit, comprising an input terminal and an output terminal, wherein the input terminal of the first comparing/detecting circuit is coupled to the first terminal of the first capacitor, and the output terminal of the first comparing/detecting circuit is coupled to the R input terminal of the S-R flip flop,wherein the output terminal of the first comparing/detecting circuit outputs a first logic pulse when a voltage of the input terminal of the first comparing/detecting circuit is lower than a first voltage; and a second delay circuit, comprising:
a second charging circuit, comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the second charging circuit is coupled to a power voltage, the control terminal of the first charging circuit is coupled to the Q′ terminal, wherein the first terminal of the second charging circuit is electrically conducted with the second terminal of the second charging circuit when the Q′ terminal outputs the first logic voltage;a second capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the second terminal of the second charging circuit, and the second terminal of the second capacitor is coupled to the common voltage;a second discharging device, comprising a first terminal and a second terminal, wherein the first terminal of the second discharging device is coupled to the second terminal of the second charging circuit, and the second terminal of the second discharging device is coupled to the common voltage; anda second comparing/detecting circuit, comprising an input terminal and an output terminal, wherein the input terminal of the second comparing/detecting circuit is coupled to the first terminal of the second capacitor, and the output terminal of the second comparing/detecting circuit is coupled to the S input terminal of the S-R flip flop, wherein the output terminal of the second comparing/detecting circuit outputs the first logic pulse when a voltage of the input terminal of the second comparing/detecting circuit is lower than a second voltage, wherein the first discharging device comprises:
a first N-type MOSFET, includes a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the gate terminal of the first N-type MOSFET receives a first bias, the first source/drain terminal of the first N-type MOSFET is coupled to the first terminal of the first discharging device, and the second source/drain terminal of the first N-type MOSFET is coupled to the second terminal of the first discharging device, wherein the first bias is generated by a bias generator, wherein the bias generator comprises:a first resistor, includes a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the power voltage;a second N-type MOSFET, includes a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the gate terminal of the second N-type MOSFET is coupled to the first source/drain terminal of the second N-type MOSFET, and the second terminal of the second N-type MOSFET is coupled to the common voltage;a third N-type MOSFET, includes a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the gate terminal of the third N-type MOSFET is coupled to the gate terminal of the second N-type MOSFET, and the second terminal of the third N-type MOSFET is coupled to the common voltage; anda second P-type MOSFET, includes a gate terminal, a first source/drain terminal and a second source/drain terminal, wherein the gate terminal of the second P-type MOSFET is coupled to the second source/drain terminal of the second P-type MOSFET and the first source/drain terminal of the third N-type MOSFET, and the first source/drain terminal of the second P-type MOSFET is coupled to the power voltage, wherein a voltage of the gate terminal of the second N-type MOSFET is the first bias, and wherein the bias generator provides the clock signal being produced substantially independent of the power voltage, process parameter and temperature. |
