BINARY FREQUENCY SHIFT KEYING WITH DATA MODULATED IN DIGITAL DOMAIN AND CARRIER GENERATED FROM INTERMEDIATE FREQUENCY

摘要

Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

主权项

1. An apparatus for binary frequency shift keying modulation, comprising:
a phase locked loop (PLL) configured to provide a high frequency clock; a digital rate converter coupled to said PLL and configured to convert said high frequency clock into first and second clock signals that each have a lower frequency than said high frequency clock, said first clock signal having only a first predetermined number of consecutive pulses within a period of time that contains only a second predetermined number of consecutive pulses of the high frequency clock, said second clock signal having only said first predetermined number of consecutive pulses within a period of time that contains only a third predetermined number of consecutive pulses of the high frequency clock, wherein said second and third predetermined numbers differ from one another and are both greater than said first predetermined number, and wherein said digital rate converter is configured to select between said first and second clock signals based on binary data values selected for transmission; a digital phase generator coupled to said digital rate converter and configured to generate a plurality of digital phase signals corresponding to a selected one of said first and second clock signals; and a driver coupled to said digital phase generator and configured to weight digital phase signals from said digital phase generator to synthesize an output waveform having binary data values modulated thereon.