Faulty core recovery mechanisms for a three-dimensional network on a processor array

摘要

Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.

主权项

1. A multidimensional switch network for a processor array, comprising:
multiple switches for routing packets between multiple core circuits of said processor array, wherein said multiple switches are organized into multiple planes; at least one redundant switch organized into at least one redundant plane; and multiple data paths interconnecting said multiple switches and said at least one redundant switch, wherein said multiple data paths include at least one redundant data path interconnecting a pair of non-neighboring switches; wherein at least one switch of said multiple switches is configurable to exchange packets with a non-neighboring switch via a redundant data path to bypass one of said multiple planes when said bypassed plane includes a component failure of said processor array, and allow recovery of said bypassed plane using said at least one redundant plane.