发明名称 System for designing a semiconductor device, device made, and method of using the system
摘要 This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.
申请公布号 US9158883(B2) 申请公布日期 2015.10.13
申请号 US201213569717 申请日期 2012.08.08
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Peng Yung-Chow;Chou Wen-Shen;Horng Jaw-Juinn
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A method of making a semiconductor device comprising: generating layout style information based on a layout design of the semiconductor device, the layout style information comprising information regarding whether an active edge cell of the semiconductor device and a non-edge cell of the semiconductor device adjacent to the active edge cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers is distributed in the active edge cell and the non-edge cell; generating array edge information based on the layout design and a schematic design of the semiconductor device; performing smart dummy insertion to selectively revise the layout design based on the layout style information and the array edge information; performing a design rule check on the revised layout design based on the layout style information and the array edge information, comprising determining whether a pattern density gradient at the active edge cell of the semiconductor device exceeds a threshold value; and repeating the revising the layout design step if the pattern density gradient at the active edge cell exceeds the threshold value, wherein at least one of the above operations is performed by a computer.
地址 TW