发明名称 |
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES |
摘要 |
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor. |
申请公布号 |
US2015287464(A1) |
申请公布日期 |
2015.10.08 |
申请号 |
US201514618815 |
申请日期 |
2015.02.10 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Yu Xiaojun;Prabhakar Venkatraman;Kouznetsov Igor G.;Hinh Long T;Jin Bo |
分类号 |
G11C16/10;G11C16/04 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
San Jose CA US |