SEMICONDUCTOR CHIP AND SYSTEM

摘要

PROBLEM TO BE SOLVED: To prevent variations in a pulse width of a second control signal from causing failed delivery of data between semiconductor chips.SOLUTION: Core chips CC0-CC3 each comprises: a TSVFIFO 42 supplying data on a bus RWBUS_CORE to a bus RWBUS_TSVFIFO, in response to a control signal DRAOTSV; a TSV buffer 43 outputting data on the bus RWBUS_TSVFIFO, in response to a control signal DRAOTSVOUT; and a phase detection circuit 48 comparing phases of the control signal DRAOTSV and the control signal DRAOTSVOUT, and outputting a phase detection result signal PD indicative of a comparison result. An interface chip IF comprises: a read control timing adjustment circuit 25 generating the control signal DRAOTSVOUT; and a delay adjustment circuit 24 adjusting, in response to the phase detection result signal PD, timing at which the read control timing adjustment circuit 25 activates the control signal DRAOTSVOUT.