| 摘要 |
An integrated circuit chip and impedance calibration method thereof, comprising at least one circuit of a single-ended structure and a first drive circuit; the first drive circuit has the same structure as the drive circuit of the at least one single-ended structure and comprises a plurality of parallel PMOS transistors and a plurality of parallel NMOS transistors; the plurality of parallel PMOS transistors are in serial connection with the plurality of parallel NMOS transistors via a first node providing signal output; after impedance calibration, the chip determines a first impedance calibration code and a second impedance calibration code, and controls the drive circuit of the at least one single-ended structure according to the calibrated first impedance calibration code and second impedance calibration code; a first reference voltage is configured as three quarters of the supply voltage VDD, and a second reference voltage is configured as one quarter of the supply voltage VDD. The integrated circuit chip and the impedance calibration method thereof are suitable for both single-ended signal output and differential signal output, and are suitable for a wide range of supply voltages. |
