主权项 |
1. A discrete-time amplifier circuit operable in a sampling phase and an amplification phase, the amplifier circuit comprising:
a plurality of switches; a first and a second capacitor; and at least one buffer amplifier having an input terminal and an output terminal, wherein:
during the sampling phase, the plurality of switches are configured to couple a first input voltage to the first capacitor and a second input voltage to the second capacitor; andduring the amplification phase, the plurality of switches are configured to couple the first and the second capacitors across the input terminal and the output terminal of the buffer amplifier to amplify a weighted sum of the first and the second input voltages. |