Parallel multiplier using a skip array and a modified Wallace tree

摘要

A parallel multiplier with skip array and modified Wallace tree comprising a modified Booth encoder (MBE) for encoding a multiplier (Y) by a modified Booth algorithm, a skip array (SAP) intended for the partial products, a modified Wallace tree (MWT) for adding up the binary bits, and a hybrid prefixed adder (HPA) for adding up two final lines, in which a fast multiplication of 0 (log n) is performed continuously without a wait condition for a carry output and the regularity of the layout of the parallel multiplier is improved so that the necessary microchip area and manufacturing costs are reduced. <IMAGE>