发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND DEPLETION-TYPE MOS TRANSISTOR
摘要 <p>A non-volatile semiconductor memory device and the depletion mode MOS transistor are provided to form the first and second transistors on the semiconductor substrate at the same time by forming the channel region and the source-drain diffusion region at the same time. A memory cell transistor equipped with a charge storing layer which is formed by interposing a gate insulating layer(25) on the semiconductor substrate is arranged inside a memory cell array. A peripheral circuit is comprised to operate the memory cell transistor. The peripheral circuit comprises at least the first transistor. The first transistor comprises a semiconductor layer of the second conductive type, a gate electrode(26), a channel region(22) of the first conductivity type and a source-drain diffusion region(21) of the first conductivity type. The first transistor includes an overlap region(24) of the first conductivity type having the third impurity concentration which is greater than the second impurity density.</p>
申请公布号 KR20090093872(A) 申请公布日期 2009.09.02
申请号 KR20090016801 申请日期 2009.02.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 GOMIKAWA KENJI;NOGUCHI MITSUHIRO
分类号 H01L27/115;H01L21/8247 主分类号 H01L27/115
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