| 摘要 |
An overlay key of a semiconductor device and a manufacturing method thereof are provided to enhance reliability by preventing an unnecessary rework process or defects of circuit patterns in an incorrect state of an overlay measurement. A main scale(410) pattern is formed on a scribe region of a semiconductor substrate. A first material layer is formed to cover the resultant including the main scale pattern. A sacrificial layer pattern is formed on the first material layer. The sacrificial layer pattern is formed with two or more line patterns which are arranged in a constant interval on the first material layer. A spacer is formed at a sidewall of the sacrificial layer pattern. The sacrificial layer pattern is removed. The material layer is patterned by using the spacer as a mask. A vernier(420) pattern including at least two or more line/space patterns is formed by patterning the material layer. The spacer is removed.
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