发明名称 |
Single transistor memory cell with reduced recombination rates |
摘要 |
A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
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申请公布号 |
US7517741(B2) |
申请公布日期 |
2009.04.14 |
申请号 |
US20050172569 |
申请日期 |
2005.06.30 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ORLOWSKI MARIUS K.;BURNETT JAMES D. |
分类号 |
H01L21/00;H01L21/84 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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