| 摘要 |
A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.
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