发明名称 TECHNIQUE FOR OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To achieve effects of improved performance and yield and reduced chip costs by improving dimensional accuracy of an electrically important portion. <P>SOLUTION: A technique for optimizing a semiconductor device manufacturing process forms a pattern based on circuit design data on a substrate through an exposure process using a photomask created from the circuit design data. The optimizing technique includes a step of weighting a difference based on electrical characteristic information extracted from the circuit design data in calculating a statistic based on distribution of the difference at plural predetermined portions between a pattern formed on the substrate by a first exposure device under a first exposure condition using the photomask and a pattern formed on the substrate by a second exposure device under a second exposure condition using the photomask; and a step (S27) of repeating the calculating while changing the second exposure conditions, and selecting an exposure condition that makes the total minimum or smaller than a predetermined reference value among different second exposure conditions, as an optimum exposure condition 21 for the second exposure device. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012160521(A) 申请公布日期 2012.08.23
申请号 JP20110017956 申请日期 2011.01.31
申请人 TOSHIBA CORP 发明人 KAJIWARA SEIKI;KOBAYASHI SACHIKO;TANAKA SATOSHI;TAKAHATA KAZUHIRO;NOJIMA SHIGEKI;KOTANI TOSHIYA;MAEDA YUKITO
分类号 H01L21/027;G03F1/68 主分类号 H01L21/027
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