Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density

摘要

An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

主权项

1. A method of making an integrated circuit substrate, comprising:
providing a core comprising a dielectric layer with a pattern of large-diameter conductive vias extending therethrough from a top side to a bottom side thereof, wherein the large-diameter conductive vias include signal-bearing vias and voltage plane vias; forming the substrate on the core by laminating a first top insulating layer on the top side of the core; further forming the substrate on the core by depositing a top transmission line reference plane metal layer on a top side of the first top insulating layer; further forming the substrate on the core by laminating a second top insulating layer on a top side of the top transmission line reference plane metal layer; and further forming the substrate on the core by forming a top signal layer on a top side of the second top insulating layer having conductive paths routed above the voltage plane vias, wherein the depositing the top transmission line reference plane metal layer defines regions devoid of metal above the signal-bearing vias so that capacitive coupling between the tops of the signal-bearing vias and the top transmission line reference plane metal layer is substantially reduced, and wherein the top transmission line reference plane metal layer does not provide power distribution within the substrate.