CLOCK DOUBLING CIRCUIT AND METHOD OF OPERATION

摘要

A clock doubler circuit includes a filtering circuit. The filtering circuit includes a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal. The third clock signal is a complementary signal to the second clock signal. The first clock signal, the second clock signal, and the third clock signal are at a first clock frequency. The second clock signal is a low pass filtered version of the first clock signal. The clock doubler circuit includes a frequency doubling circuit. The frequency doubling circuit includes a first input to receive the second clock signal and a second input to receive the third clock signal. The frequency doubling circuit includes an output node. The output node provides a fourth clock signal at a second clock frequency that is twice the first clock frequency.

主权项

1. A clock doubler circuit comprising:
a filtering circuit including a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal, wherein the third clock signal is a complementary signal to the second clock signal, wherein the first clock signal, the second clock signal, and the third clock signal are at a first clock frequency, wherein the second clock signal is a low pass filtered version of the first clock signal; a frequency doubling circuit including:
a first input to receive the second clock signal and a second input to receive the third clock signal;an output node, the output node providing a fourth clock signal at a second clock frequency that is twice the first clock frequency.