发明名称 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
摘要 An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.
申请公布号 US9148520(B2) 申请公布日期 2015.09.29
申请号 US201314136203 申请日期 2013.12.20
申请人 Intel Corporation 发明人 Dzik Dariusz;Barazesh Bahman
分类号 H04M3/00;H04M7/12;H04Q1/457 主分类号 H04M3/00
代理机构 Green, Howard & Mughal LLP 代理人 Green, Howard & Mughal LLP
主权项 1. An apparatus comprising: a decision circuit configured to generate a confirmation signal in response to a first lock signal and a second lock signal; a detector circuit configured to generate said first lock signal in response to a filtered version of an input signal being above a threshold; and a processing circuit configured to generate said second lock signal in response to a power signal received from said detector circuit, wherein said processing circuit generates said second lock signal by analyzing a rising edge of a frequency power envelope of said power signal.
地址 Santa Clara CA US