发明名称 |
DC-DC converter and audio output unit |
摘要 |
A DC-DC converter includes a first capacitor which can be charged by a power-supply voltage; a second capacitor that generates the output voltage using electric charge previously discharged by the first capacitor; a comparator that compares the output voltage with a reference voltage and outputs a comparison signal that shows whether the output voltage is below the reference voltage; multiple switches that switch to allow the first capacitor either to be charged or to discharge its charge to the second capacitor, and a controller that controls the switch timing of the multiple switches on the basis of the comparison signal. |
申请公布号 |
US9143095(B2) |
申请公布日期 |
2015.09.22 |
申请号 |
US201213605935 |
申请日期 |
2012.09.06 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Takida Takayuki |
分类号 |
H03F99/00;G05F3/04;G05F3/08;H03F3/181;H02M3/07 |
主分类号 |
H03F99/00 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A DC-DC converter comprising:
a first capacitor configured to be charged by a power-supply voltage, a second capacitor configured to provide an output voltage, the output voltage being caused by electric charge previously discharged by the first capacitor; a comparator configured to compare the output voltage with a first reference voltage, and to output a first comparison signal indicative of whether the output voltage is greater or less than the first reference voltage; a switch configured to allow the first capacitor to be charged, and also configured to allow the first capacitor to discharge to the second capacitor; and a controller configured to control switch timing of the switch, the controlling being based on the first comparison signal; the controller further being configured to randomize the times of a cycle at which the first capacitor is charged; wherein the controller comprises a duty selector configured to randomly select a clock signal from amongst multiple clock signals of a same frequency, the multiple clock signals being of different duty ratios; wherein the switch is further configured to switch based on the clock signal randomly selected by the duty selector; and wherein the duty selector is further configured to randomly select a clock signal by sending a first random bit stream to a first multiplexer associated with clock signals having different duty ratios. |
地址 |
Tokyo JP |