发明名称 |
MATRIX AND COMPRESSION-BASED ERROR DETECTION |
摘要 |
Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor. |
申请公布号 |
US2015260792(A1) |
申请公布日期 |
2015.09.17 |
申请号 |
US201414205910 |
申请日期 |
2014.03.12 |
申请人 |
International Business Machines Corporation |
发明人 |
Drapala Garrett M.;Strait Gary E. |
分类号 |
G01R31/317;G01R31/3177 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
1. A computer system for matrix and compression-based error detection, the system comprising:
a circuit under test that outputs a plurality of output bits, the plurality of output bits of the circuit under test arranged in a matrix comprising a plurality of rows and a plurality of columns, wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row; a first compressor comprising a first plurality of summing modules, each of the first plurality of summing modules coupled to a respective row of the matrix; and a second compressor comprising a second plurality of summing modules, each of the second plurality of summing modules coupled to a respective column of the matrix, the system configured to perform a method comprising:
summing, by each the first plurality of summing modules, the output bits in the summing module's respective row of the matrix;summing, by each the second plurality of summing modules, the output bits in the summing module's respective column of the matrix; anddetermining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor. |
地址 |
Armonk NY US |