SEMICONDUCTOR DEVICE

摘要

An n− type diffusion region surrounds a high side well region and is electrically isolated from a low side region. In the n− diffusion region formed are a first p type diffusion region and the second p type diffusion region separated with each other. The first p type diffusion region composes a double RESURF structure in an nch MOSFET in the level shift-up circuit, and in a high voltage junction terminating structure. The second p type diffusion region composes a double RESURF structure of a pch MOSFET of a level shift-down circuit. The impurity concentration of the n− type diffusion region is in the range of 1.3×1012/cm2 to 2.8×1012/cm2. The impurity concentration of the first p type diffusion region and the impurity concentration of the second p type diffusion region are in the range of 1.1×1012/cm2 to 1.4×1012/cm2.

主权项

1. A semiconductor device comprising:
a first field effect transistor of a first conductivity type and including:
a first semiconductor region of a second conductivity type disposed on a semiconductor substrate of a first conductivity type or formed on a surface layer of the semiconductor substrate of the first conductivity type,a second semiconductor region of a first conductivity type selectively formed on a surface layer of the first semiconductor region;a third semiconductor region of the first conductivity type selectively formed on the surface layer of the first semiconductor region and spaced apart from the second semiconductor region;a first gate electrode formed on a surface of a portion of the first semiconductor region disposed between the second semiconductor region and the third semiconductor region with an intercalated first gate insulating film;a fourth semiconductor region of the first conductivity type selectively formed in the second semiconductor region;a first electrode connected to the third semiconductor region; anda second electrode connected to the fourth semiconductor region; and a device element including a fifth semiconductor region of the first conductivity type formed on the surface layer of the first semiconductor region, spaced apart from the second semiconductor region and the third semiconductor region, the device element being isolated from the first field effect transistor by a part of the first semiconductor region disposed between the second semiconductor region and the fifth semiconductor region, wherein an impurity concentration of the first semiconductor region disposed between the second semiconductor region and the semiconductor substrate is in the range of 1.3×1012/cm2 to 2.8×1012/cm2, and an impurity concentration of the second semiconductor region is in the range of 1.1×1012/cm2 to 1.4×1012/cm2.