Semiconductor device including a high voltage P-channel transistor and method for manufacturing the same

摘要

A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region.

主权项

1. A semiconductor device having a high voltage p-channel transistor, the high voltage p-channel transistor comprising:
a semiconductor substrate having a main surface and a p-type region therein: a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region located in a way to adjoin the p-type well region in a direction along the main surface, having a second p-type impurity region to obtain a source electrode; a gate electrode located between the first p-type impurity region and the second p-type impurity region in the direction along the main surface; and a p-type buried channel located over the n-type well region, extending along the main surface, wherein a border between a side of the n-type well region and a side of the p-type well region is located between the first p-type impurity region and an end of the gate electrode nearer to the first p-type impurity region, one end of the p-type buried channel is joined to the second p-type impurity region, and the other end of the p-type buried channel on the side of the first p-type impurity region is located nearer to the first p-type impurity region than one end of the gate electrode, the one end of the gate electrode being located on the side of the first p-type impurity region, and the semiconductor device further comprises a p-type low doped region between the p-type buried channel and the border, a p-type impurity concentration of the p-type low doped region being lower than that of the p-type buried channel.