Display memory, driver circuit, display, and portable information device

摘要

A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

主权项

1. A driver circuit which drives a plurality of pixels arrayed in a matrix in a display, comprising:
a first line latch which stores pixel data corresponding to a horizontal line of pixels from the matrix of pixels in the display in a display memory; a driving unit which writes the pixel data supplied from said first line latch into said display memory via a controller unit; and a second line latch which buffers the pixel cell data corresponding to the horizontal line of pixels stored in the display memory for output to the display, wherein,
the driving unit is configured to read the pixel data from said display memory, and to output the pixel data to said controller unit via the first line latch,said first line latch designates which pixel data in the first line latch is written into the display memory,said driving unit writes only the pixel data held in said first line latch designated for writing into the display memory, andsaid display memory includes:
(1) a plurality of memory cells arrayed in a matrix corresponding to the matrix array of said plurality of pixels, each memory cell having a first storage node and a second storage node configured to hold states of a complementary first level and second level,(2) a first read port which reads the stored data of said first storage node of each memory cell,(3) a second read port which reads the stored data of said second storage node of each memory cell, and(4) a write port which writes pixel data for driving corresponding pixel cells of the matrix of said display into said memory cells.