INTERRUPTIBLE STORE EXCLUSIVE

摘要

In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

主权项

1. A system on a chip comprising:
a memory; a memory bus communicatively coupled to the memory; and a processor communicatively coupled to the memory via the memory bus, the processor including circuitry for providing store exclusive functionality comprising:
a store exclusive initialize (STREX_INIT) instruction, the STREX_INIT instruction operable to initiate an exclusive store transaction to a location in the memory;a store exclusive synchronize (STREX_SYNC) instruction, the STREX_SYNC instruction operable to monitor an XWAVAIL indicator, the XWAVAIL indicator operable to indicate that an XWRESULT response to the STREX_INIT primitive is available, the XWRESULT response operable to indicate whether the exclusive store transaction to the location in memory was successful.