VACUUM LAMINATION APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

摘要

The present invention relates to a vacuum lamination apparatus used when manufacturing a semiconductor device. The vacuum lamination apparatus comprises a frame mechanism enclosing at least a side surface of a support base material attaching encapsulation material wherein a thermosetting resin layer as an encapsulation material is layered on a support base material. The frame mechanism comprises a maintaining means to maintain a substrate on which a semiconductor element is loaded or a wafer on which the semiconductor element is formed while arranging the substrate or the wafer to oppose the thermosetting resin layer by disposing a space in the thermosetting resin layer of the support base material attaching encapsulation material. The vacuum lamination apparatus vacuum-laminates the support base material attaching encapsulation material enclosed by the frame mechanism with the substrate or the wafer. Accordingly, specifically, even when a substrate (or a wafer) of a large surface area is used, creation of a void in the resin layer and bending of the substrate (or the wafer) can be suppressed, and a semiconductor device on which a resin layer is formed with high precision can be manufactured with low costs.