Generation of simulated errors for high-level system validation

摘要

A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

主权项

1. A device comprising:
logic operable to request information concerning an address of a storage, the requested information corresponding to original data of the storage; and an integrated circuit operably coupled to the processor, the integrated circuit operable to:
intercept the original data,virtualize an error in the original data by generating modified data, andgenerate an interrupt according to the virtualized error.