Method and apparatus for data reception in high-speed applications

摘要

A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

主权项

1. A data receiver comprising:
an analog-to-digital converter configured to convert an analog signal into a digital signal based at least in part on a first sampling phase; a non-Viterbi decoder configured to decode the digital signal into a first set of decoded bits using a non-Viterbi tree search algorithm and outputting the first set of decoded bits on a feedback signal path; wherein the feedback signal path is connected between the non-Viterbi decoder and a timing recover module; a Viterbi decoder configured to decode the digital signal from the analog-to-digital converter into a second set of decoded bits with a Viterbi detection algorithm; wherein a decoded output from the data receiver is the second set of decoded bits from the Viterbi decoder; wherein the timing recovery module is configured to:
calculate an error value for the digital signal using the first set of decoded bits from the feedback signal path while not using the second set of decoded bits from the Viterbi decoder; andcalculate a second sampling phase based, at least in part on the calculated error value, wherein the second sampling phase is provided to the analog-to-digital converter to be used for converting a subsequently received analog signal into a digital signal; wherein the non-Viterbi decoder is configured to perform the non-Viterbi tree search algorithm comprising:
calculating path metrics for potential states of a tree for determining a decoded bit; anddiscarding portions of the tree based at least in part on the path metrics until the digital signal is decoded.