SEMICONDUCTOR DEVICE

摘要

A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

主权项

1. A semiconductor device comprising:
a semiconductor substrate having a main surface and a back surface; a drain region of a first conduction type formed at the back surface of the semiconductor substrate; an epitaxial layer of the first conduction type on the drain region, wherein impurity concentration of the epitaxial layer is lower than that of the drain region; a base region of a second conduction type opposite to the first conduction type formed in the epitaxial layer and provided over the drain region; a plurality of source regions of the first conduction type(N) provided in the base region; an outer peripheral well region of the second conduction type provided in the epitaxial layer so as to cover the outer peripheral end of the base region and having a concentration of impurity lower than that of the base region; a buried electrode situated in the base region in a plan view, and buried in the base region and the epitaxial layer in a cross sectional view; a plurality of gate electrodes situated in the base region in a plan view, electrically connected to the buried electrode, and buried in the base region and the epitaxial layer in a cross sectional view so as to be adjacent to the source regions respectively; a gate interconnect provided over the main surface of the semiconductor substrate so as to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode by way of a first contact plug; and a grounding electrode provided over the main surface of the semiconductor substrate and connected by way of a second contact plug to a portion of the outer peripheral well region apart from the gate interconnect in a plan view, wherein a buried electrode is apart from the outer peripheral well region.