Computer Hardware Architecture and Data Structures for Packet Binning to Support Incoherent Ray Traversal

摘要

A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

主权项

1. Digital circuitry to create a database of objects in a scene for ray tracing comprising:
a plurality of data arrays in a first memory, each data array corresponding to a cell comprising the scene, each data array operative to receive and store data for objects in the scene that are at least partially contained by the cell corresponding to said each data array; a plurality of pointer packet registers, each pointer packet register corresponding to a cell comprising the scene and operative to receive and store pointers to areas of memory in a data packet memory separate from the first memory; and control logic circuitry configured to control operation of the data arrays and pointer packet registers while the data for the objects are being stored in the data arrays, wherein the control logic circuitry:
(i) moves data from a given data array that is on-chip with respect to the digital circuitry into an area of memory in the data packet memory that is off-chip with respect to the digital circuitry when the given data array is in a full condition;(ii) stores a pointer to the area of memory in the data packet memory into one of the pointer packet registers, wherein said one of the pointer packet registers and the given data array correspond to the same cell; and(iii) moves data from a given pointer packet register that is on-chip with respect to the digital circuitry into a corresponding pointer packet memory that is off-chip with respect to the digital circuitry when the given pointer packet register is in a full condition, wherein the control logic circuitry is distributed among the data arrays and the pointer packet registers so that the data arrays operate independently of each other and the pointer packet registers operate independently of each other.