发明名称 |
Method of manufacturing a lateral semiconductor device |
摘要 |
<p>A method of forming a semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises providing a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a method of manufacturing a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well and with an extended drift region is disclosed.</p> |
申请公布号 |
EP1914797(B1) |
申请公布日期 |
2015.08.12 |
申请号 |
EP20070011477 |
申请日期 |
2007.06.12 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HUANG, TSUNG-YI;CHIANG, PUO-YU;LIU, RUEY-HSIEN;HSU, SHUN-LIANG |
分类号 |
H01L21/336;H01L29/06;H01L29/08;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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