Bidirectional shift register and image display device using the same

摘要

A plurality of cascaded unit register circuits (38) which comprises a bidirectional shift register (30) include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse P k in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which P k - 1 and P k+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which P k - 2 and P k+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.