摘要 |
A control electrode (GE1) is formed at a lower section in a trench (TR1) that is formed in a semiconductor substrate (SUB), and a gate electrode (GE2) is formed at an upper section in the trench (TR1). Insulating films (G1) are formed between the side walls of the trench (TR1) and the control electrode (GE1) and between the bottom surface of the trench and the control electrode, insulating films (G2) are formed between the side walls of the trench (TR1) and the gate electrode (GE2), and an insulating film (G3) is formed between the control electrode (GE1) and the gate electrode (GE2). In a region adjacent to the trench (TR1), there are an n+ type semiconductor region (NR) for a source, a p type semiconductor region (PR) for forming a channel, and a semiconductor region for a drain. Wiring connected to the control electrode (GE1) is not connected to wiring connected to the gate electrode (GE2), and is not connected to wiring connected to the n+ type semiconductor region (NR) for the source. |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
NUMABE, HIDEO;SHIRAI, NOBUYUKI;KATO, HIROKAZU;UNO, TOMOAKI;UMEZU, KAZUYUKI |