MPS-C2 semiconductor device having shorter supporting posts

摘要

Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.

主权项

1. A MPS-C2 semiconductor device comprising:
a chip having an active surface and a plurality of bonding pads on the active surface; a wafer-level packaging layer formed on the active surface, wherein the bonding pads are reentrant from the wafer-level packaging layer; a patterned UBM layer including a plurality of UBM pads and at least a first UBM island, wherein the UBM pads are respectively disposed on the bonding pads and the first UBM island is disposed on the wafer-level packaging layer far away from the bonding pads, wherein a first island area of the first UBM island is at least four times greater than the unit area of the UBM pads on the corresponding bonding pads; a plurality of I/O pillars disposed on the corresponding UBM pads in a one-to-one relationship, wherein each I/O pillar has a first top jointing surface; and a plurality of first supporting pillars disposed on the first UBM island in a many-to-one relationship, wherein there are two or more first supporting pillars disposed on each first UBM island, and each first supporting pillar has a second top jointing surface, wherein a second unit footprint of the first supporting pillars on the first UBM island is smaller than a first unit footprint of the I/O pillars on the UBM pads to compensate the jointing height difference between the second top jointing surfaces and the first top jointing surfaces.